1. Field of the Invention
The present invention relates to a video signal memory equipment for storing video data of non-standard video signal in a first in first out (FIFO) memory.
2. Description of the Related Art
Recently, various effects are realized on the screen by signal processing of video information. In this case, the means for storing once the video signal in the memory, and then processing the stored video information is widely employed.
Signal processing of video information is generally done on the video data sampling the video signal by the clock synchronized with the burst signal clock, that is, the clock locked in burst signal clock. After detecting the starting point of video signals of one screen by the input of a vertical synchronizing signal, the starting point of brightness signals is detected by the successive input of horizontal synchronizing signal, and from that moment the brightness signals are sequentially sampled by the clock locked in burst signal clock to obtain the image data for one screen, and the image data are sequentially written into the memory. In this case, there are standard video signals of which relative positions of vertical synchronizing signals and horizontal synchronizing signals and the signal width are standard as defined as the broadcasting method, and defective video signals, such as video signals reproduced from a video tape recorder. The video signals reproduced from a video tape recorder often become defective video signals by operation fluctuations of mechanical elements. The number of video data that can be obtained by sampling the video signals by the clock locked in burst signal clock of 4 fsc (fsc: burst signal clock frequency) varies in a range of about 910.+-.30 in the NTSC system, and 135.+-.30 in the PAL system,in one horizontal scanning period of non-standard video signals.
Therefore, for example, when synthesizing a screen 1 and a next screen, or when synthesizing a screen of non-standard video signals on a screen of standard video signals, since the number of data in the horizontal scanning period varies between two screens, the video data do not correspond to each other correctly. FIG. 7 is a schematic diagram in which video data of one screen of defective video signals fluctuating in the interval of horizontal synchronizing signals are sequentially written into a memory, the number of video data in one horizontal scanning period is 910, which are sequentially read out, and caused to correspond to the video data of one screen of standard signals of which number of video data in one horizontal scanning period is 910 in all cases. As known from the diagram, when video data are processed between two screens, an effect of horizontal synchronizing signal waveform appears in the image, and a defect is formed on the image. To solve such problem, by using the means for dividing the video data in every horizontal scanning period, writing into the memory and reading out in every horizontal scanning period, as shown in FIG. 7(b), every video data is reproduced so as to correspond to the original positions sampled in the horizontal scanning period. To realize such video signal memory equipment, the means for dividing the video data in every horizontal synchronizing signal by the address, writing into the memory and reading out is employed.
The conventional video signal memory equipment performing in such manner is explained below. FIG. 6 is a block diagram of constitution of a conventional video signal memory equipment using the field memory for input and output of data by address. In the diagram, numeral 6 is an address generating circuit for generating writing or reading address of a field memory 7 on the basis of an input horizontal synchronizing signal, and 7 is a field memory for writing or reading data according to the address.
Thus composed video signal memory equipment operates as follows. The address generating circuit 6 generates addresses in the Y-axis direction (Y-addresses) corresponding to the numbers of the horizontal scanning periods, and addresses in the X-axis direction (X-addresses) corresponding to the numbers of video data on the horizontal scanning period, and a set of Y-address and X-address is produced as address q to the field memory 7 by parallel data of plural bits. For example, supposing the Y-addresses in each horizontal scanning period to be Y1, Y2, . . . and the X-addresses of each video data in the horizontal scanning period to be X1, X2, . . . the address generating circuit 6, after detecting the start of video signal of one screen by the input of a vertical synchronizing signal, with Y-address being Y1, counts up the X-address from X1 to X2, . . . sequentially in ever clock from the input moment of the horizontal synchronizing signal, while the field memory 7 sequentially writes the video data of horizontal scanning period according to the address. The address generating circuit 6 returns the X-address to X1 on the input moment of next horizontal synchronizing signal, and starts to count up X1, X2, . . . , and with the Y-address being Y2, the field memory 7 writes sequentially the video data of the horizontal scanning period according to the address. In this way, the video data for one screen are written into the field memory 7. When reading out the video data stored in the field memory 7, the address generating circuit 6 counts up the Y-address from Y1 to Y2, . . . on every input of horizontal synchronizing signal, and at every Y-address, moreover, the X-addresses are generated sequentially as X1, X2, . . . , and the field memory 7 produces the image data in each horizontal scanning period according to the address.
In this way, by writing and reading by dividing the video data of each horizontal scanning period in every horizontal scanning period, as shown in FIG. 7(b), it is reproduced so that the video data being readout corresponds to the sampling sequence of each horizontal scanning period, and corresponds to the video data of other video signals.
In such conventional constitution, however, the address generating circuit 6 is necessary, and many connection pins are needed in order to transmit the address q, which resulted in a large circuit size.
It is hence a primary object of the invention to solve the problem by presenting a video signal memory equipment small in a circuit size.